1. Field of the Invention
The present invention relates generally to memory cell structures employed within semiconductor integrated circuit microelectronic fabrications. More particularly, the present invention relates to methods for forming memory cell structures employed within semiconductor integrated circuit microelectronic fabrications.
2. Description of the Related Art
Semiconductor integrated circuit microelectronic fabrications are formed from semiconductor substrates within and upon which are formed semiconductor devices, and over which are formed patterned conductor layers which are separated by dielectric layers.
Common in the art of semiconductor integrated circuit microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic memory fabrication, is the use and the fabrication of memory cell structures, and in particular dynamic random access memory (DRAM) cell structures. Dynamic random access memory (DRAM) cell structures typically comprise at least one field effect transistor (FET) device formed within and upon a semiconductor substrate, where one of a pair of source/drain regions within the field effect transistor (FET) device has formed thereover and electrically connected therewith a storage capacitor. Within a dynamic random access memory (DRAM) cell structure, a gate electrode of the field effect transistor (FET) device serves as a wordline which provides a switching function for charge introduction into and retrieval from the storage capacitor, while the other of the pair of source/drain regions within the field effect transistor (FET) device serves as a contact for a bitline conductor stud layer which introduces or retrieves charge with respect to the storage capacitor.
While the dynamic random access memory (DRAM) cell structure has clearly become ubiquitous in the art of semiconductor integrated circuit microelectronic memory fabrication, and is thus essential in the art of semiconductor integrated circuit microelectronic fabrication, the dynamic random access memory (DRAM) cell structure is nonetheless not entirely without problems in the art of semiconductor integrated circuit microelectronic memory fabrication.
In that regard, as semiconductor integrated circuit microelectronic fabrication integration levels have increased and semiconductor device and patterned conductor layer dimensions have decreased, it has become increasingly difficult in the art of semiconductor integrated circuit microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic memory fabrication, to readily form dynamic random access memory (DRAM) cell structures with enhanced reliability and enhanced performance.
It is thus desirable in the art of semiconductor integrated circuit microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic memory fabrication, to provide methods and materials through which there may readily be formed, with enhanced reliability and enhanced performance, dynamic random access memory (DRAM) cell structures.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed in the art of semiconductor integrated circuit microelectronic fabrication for forming, with desirable properties, dynamic random access memory (DRAM) cell structures.
Included among the methods, but not limited among the methods, are methods disclosed within: (1) Dennison, in U.S. Pat. No. 5,362,666 (a method for forming a capacitor and bitline structure within a dynamic random access memory (DRAM) cell structure for use within a semiconductor integrated circuit microelectronic memory fabrication, with enhanced bitline stud layer reliability and performance, by forming a bitline contact via through a capacitor plate layer which is spaced from a bitline contact region by a capacitor node dielectric layer); (2) Huang, in U.S. Pat. No. 6,127,260 (a method for forming a capacitor and peripheral conductor contact structure within a dynamic random access memory (DRAM) cell structure for use within a semiconductor integrated circuit microelectronic memory fabrication, with enhanced peripheral contact structure reliability, by forming a peripheral contact via in multiple vertical stages, where at least one stage is formed with a xe2x80x9cTxe2x80x9d shape); and (3) Lee et al., in U.S. Pat. No. 6,136,695 (a method for forming a self aligned contact (SAC) structure which may be used as a bitline contact structure within a dynamic random access memory (DRAM) cell structure for use within a semiconductor integrated circuit microelectronic memory fabrication, with enhanced reliability, by forming a contact spacer layer subsequent to, rather than prior to, forming a patterned premetal dielectric (PMD) layer which accesses a contact region).
Desirable in the art of semiconductor integrated circuit microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic memory fabrication, are additional methods and materials which may be employed for forming, with enhanced reliability and enhanced performance, dynamic random access memory (DRAM) cell structures.
It is towards the foregoing object that the present invention is directed.
A first object of the invention is to provide a method for forming a dynamic random access memory (DRAM) cell structure within a semiconductor integrated circuit microelectronic fabrication.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the dynamic random access memory (DRAM) cell structure is formed with enhanced reliability and enhanced performance.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for forming a contact via.
To practice the method of the present invention, there is first provided a substrate having formed therein a contact region. There is also formed over the substrate a pair of topographic structures which is separated by the contact region. There is then formed upon the substrate and the pair of topographic structures a blanket conformal isolation layer having an upper region formed upon the pair of topographic structures and a lower region formed interposed between the pair of topographic structures and over the contact region. There is then formed upon the blanket conformal isolation layer a blanket variable thickness masking layer having a greater thickness upon the upper region of the blanket conformal isolation layer than upon the lower region of the blanket conformal isolation layer. Finally, there is then etched completely through the blanket variable thickness masking layer and the blanket conformal isolation layer at the lower region of the blanket conformal isolation layer but not,the upper region of the blanket conformal isolation layer to form a pair of patterned conformal isolation layers and patterned variable thickness masking layers which define a contact via exposing the contact region.
The present invention may be employed for forming as the contact via in accord with the present invention a bitline contact via within a memory cell structure, such as a dynamic random access memory (DRAM) memory cell structure.
The present invention provides a method for forming a dynamic random access memory (DRAM) cell structure within a semiconductor integrated circuit microelectronic fabrication, wherein the dynamic random access memory (DRAM) cell structure is formed with enhanced reliability and enhanced performance.
The present invention realizes the foregoing object when forming a bitline contact via within the dynamic random access memory (DRAM) cell structure a self aligned masking method which employs formed upon a pair of topographic structures formed upon a substrate and separated by a contact region formed within the substrate: (1) a blanket conformal isolation layer, in turn having formed thereupon; (2) a blanket variable thickness masking layer having a greater thickness upon the blanket conformal isolation layer over the pair of topographic structures than interposed between the pair of topographic structures. Thus, there may be completely etched through the blanket variable thickness masking layer and the blanket conformal isolation layer interposed between the pair of topographic structures, but not completely through the blanket variable thickness masking layer or blanket conformal isolation layer over the pair of topographic structures, to form a pair of patterned conformal isolation layers and a pair of patterned variable thickness masking layers which define a contact via accessing the contact region.
The method of the present invention is readily commercially implemented.
The present invention employs methods and materials as are generally known in the art of semiconductor integrated circuit microelectronic fabrication, but employed within the context of specific process orderings and specific materials limitations to provide the method of the present invention. Since it is thus at least in part a specific process ordering and a specific materials limitation which provide at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.